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1 features ? 2.7v to 3.6v read/write ? access time - 90 ns ? sector erase architecture C thirty 32k word (64k byte) sectors with individual write lockout C eight 4k word (8k byte) sectors with individual write lockout C two 16k word (32k byte) sectors with individual write lockout ? fast word program time - 20 m m m m s ? fast sector erase time - 200 ms ? dual plane organization, permitting concurrent read while program/erase C memory plane a: eight 4k word, two 16k word and six 32k word sectors C memory plane b: twenty-four 32k word sectors ? erase suspend capability C supports reading/programming data from any sector by suspending erase of any different sector ? low power operation C 25 ma active C10 m m m m a standby ? data polling, toggle bit, ready/busy for end of program detection ? optional v pp pin for fast programming ? reset input for device initialization ? sector program unlock command ? tsop, cbga, and m m m m bga package options ? top or bottom boot block configuration available description the at49bv16x4(t) is 2.7 to 3.6 volt 16-megabit flash memory organized as 1,048,576 words of 16 bits each or 2,097,152 bytes of 8 bits each. the x16 data appears on i/o0 - i/o15; the x8 data appears on i/o0 - i/o7. the memory is divided into 40 blocks for erase operations. the device is offered in 48-pin tsop and 48-ball m bga packages. the device has ce , and oe control signals to avoid any bus con- tention. this device can be read or reprogrammed using a single 2.7v power supply, making it ideally suited for in-system programming. rev. 0925bC05/98 AT49BV1604 16-megabit (1m x 16/2m x 8) 3-volt only flash memory AT49BV1604 AT49BV1604t at49bv1614 at49bv1614t advance information at49bv16x4(t) pin configurations pin name function a0 - a19 addresses ce chip enable oe output enable we write enable reset reset rdy/busy ready/busy output v pp optional power supply for faster program/erase operations i/o0 - i/o14 data inputs/outputs i/o15 (a-1) i/o15 (data input/output, word mode) a-1 (lsb address input, byte mode) byte selects byte or word mode nc no connect v ccq output power supply dc dont connect (continued)
at49bv16x4(t) 2 the device powers on in the read mode. command sequences are used to place the device in other operation modes such as program and erase. the device has the capability to protect the data in any sector. once the data protection for a given sector is enabled, the data in that sector cannot be changed using input levels between ground and v cc . the device is segmented into two memory planes. reads from memory plane b may be performed even while pro- gram or erase functions are being executed in memory plane a and vice versa. this operation allows improved system performance by not requiring the system to wait for a program or erase operation to complete before a read is performed. to further increase the flexibility of the device, it contains an erase suspend feature. this feature will put the erase on hold for any amount of time and let the user read data from or program data to any of the remaining sectors within the same memory plane. there is no reason to suspend the erase operation if the data to be read is in the other memory plane. the end of a program or an erase cycle is detected by the ready/busy pin, data polling, or by the toggle bit. a v pp pin is provided to improve program/erase times at lower supply voltages. this pin does not need to be uti- lized. if it is not used the pin should be connected to ground or v cc . to take advantage of faster programming, the pin should supply 5.0 volts during program and erase opera- tions. tsop top view type 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a15 a14 a13 a12 a11 a10 a9 a8 nc nc we reset vpp nc a19 a18 a17 a7 a6 a5 a4 a3 a2 a1 a16 vccq gnd i/o15 i/o7 i/o14 i/o6 i/o13 i/o5 i/o12 i/o4 vcc i/o11 i/o3 i/o10 i/o2 i/o9 i/o1 i/o8 i/o0 oe gnd ce a0 cbga top view 1 2 3 4 5 6 h gfedcb vss i/o1 i/o3 i/o4 i/o6 vss oe i/o9 i/o11 vcc i/o13 i/o15 /a-1 ce i/o8 i/o10 i/o12 i/o14 byte a0 i/o0 i/o2 i/o5 i/o7 a16 a1 a5 nc a19 a11 a15 a2 a6 a18 nc a10 a14 a4 a17 nc reset a8 a12 a3 a7 rdy/busy we a9 a13 a m bga top view (ball down) a b c d e f 1 234567 a13 a14 a15 a16 vccq gnd a11 a10 a12 i/o14 i/o15 i/o7 a8 we a9 i/o5 i/o6 i/o13 vpp rst nc i/o11 i/o12 i/o4 nc a18 nc i/o2 i/o3 vcc a19 a17 a6 i/o8 i/o9 i/o10 a7 a5 a3 ce i/o0 i/o1 a4 a2 a1 a0 gnd oe 8 tsop top view type 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a15 a14 a13 a12 a11 a10 a9 a8 a19 nc we reset vpp nc rdy/busy a18 a17 a7 a6 a5 a4 a3 a2 a1 a16 byte gnd i/o15/a-1 i/o7 i/o14 i/o6 i/o13 i/o5 i/o12 i/o4 vcc i/o11 i/o3 i/o10 i/o2 i/o9 i/o1 i/o8 i/o0 oe gnd ce a0 AT49BV1604(t) at49bv1614(t)
at49bv16x4(t) 3 a six byte command (bypass unlock) sequence to remove the requirement of entering the three byte program sequence is offered to further improve programming time. after entering the six byte code, only single pulses on the write control lines are required for writing into the device. this mode (single pulse byte/word program) is exited by powering down the device, or by pulsing the reset pin low and then bringing it back to v cc . erase and erase sus- pend/resume commands will not work while in this mode; if entered they will result in data being programmed into the device. it is not recommended that the six byte code reside in the software of the final product but only exist in external programming code. the byte pin controls whether the device data i/o pins operate in the byte or word configuration. if the byte pin is set at logic 1, the device is in word configuration, i/o0- i/o15 are active and controlled by ce and oe . if the byte pin is set at logic 0, the device is in byte con- figuration, and only data i/o pins i/o0-i/o7 are active and controlled by ce and oe . the data i/o pins i/o8-i/o14 are tri-stated, and the i/o15 pin is used as an input for the lsb (a-1) address function. block diagram device operation read: the at49bv16x4(t) is accessed like an eprom. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins are asserted on the outputs. the outputs are put in the high impedance state whenever ce or oe is high. this dual-line control gives designers flexibility in preventing bus conten- tion. command sequences: when the device is first pow- ered on it will be reset to the read or standby mode depending upon the state of the control line inputs. in order to perform other device functions, a series of command sequences are entered into the device. the command sequences are shown in the command definitions table (i/o8 - i/o15 are don't care inputs for the command codes). the command sequences are written by applying a low pulse on the we or ce input with ce or we low (respec- tively) and oe high. the address is latched on the falling edge of ce or we , whichever occurs last. the data is latched by the first rising edge of ce or we . standard microprocessor write timings are used. the address loca- tions used in the command sequences are not affected by entering the command sequences. identifier register status register data comparator output multiplexer output buffer input buffer command register data register y-gating write state machine program/erase voltage switch ce we oe reset byte rdy/busy vpp vcc gnd y-decoder x-decoder input buffer address latch i/o0 - i/o15/a-1 a0 - a19 plane b sectors plane a sectors
at49bv16x4(t) 4 reset: a reset input pin is provided to ease some sys- tem applications. when reset is at a logic high level, the device is in its standard operating mode. a low level on the reset input halts the present device operation and puts the outputs of the device in a high impedance state. when a high level is reasserted on the reset pin, the device returns to the read or standby mode, depending upon the state of the control inputs. by applying a 12v 0.5v input signal to the reset pin any sector can be reprogrammed even if the sector lockout feature has been enabled (see sector programming lockout override section). erasure: before a byte/word can be reprogrammed, it must be erased. the erased state of memory bits is a logi- cal 1. the entire device can be erased by using the chip erase command or individual sectors can be erased by using the sector erase commands. chip erase: the entire device can be erased at one time by using the 6-byte chip erase software code. after the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. the maximum time to erase the chip is t ec . if the sector lockout has been enabled, the chip erase will not erase the data in the sector that has been locked; it will erase only the unprotected sectors. after the chip erase, the device will return to the read or standby mode. sector erase: as an alternative to a full chip erase, the device is organized into forty sectors (sa0 - sa39) that can be individually erased. the sector erase command is a six bus cycle operation. the sector address is latched on the falling we edge of the sixth cycle while the 30h data input command is latched on the rising edge of we . the sector erase starts after the rising edge of we of the sixth cycle. the erase operation is internally controlled; it will automati- cally time to completion. the maximum time to erase a sec- tion is t sec . when the sector programming lockout feature is not enabled, the sector will erase (from the same sector erase command). once a sector has been protected, data in the protected sectors cannot be changed unless the reset pin is taken to 12v 0.5v. an attempt to erase a sector that has been protected will result in the operation terminating in 2 m s. byte/word programming: once a memory block is erased, it is programmed (to a logical 0) on a byte-by-byte or on a word-by-word basis. programming is accomplished via the internal device command register and is a 4-bus cycle operation. the device will automatically generate the required internal program pulses. any commands written to the chip during the embedded programming cycle will be ignored. if a hardware reset hap- pens during programming, the data at the location being programmed will be corrupted. please note that a data 0 cannot be programmed back to a 1; only erase operations can convert 0s to 1s. programming is completed after the specified t bp cycle time. the data polling feature or the toggle bit feature may be used to indicate the end of a program cycle. sector programming lockout: each sector has a programming lockout feature. this feature prevents pro- gramming of data in the designated sectors once the fea- ture has been enabled. these sectors can contain secure code that is used to bring up the system. enabling the lock- out feature will allow the boot code to stay in the device while data in the rest of the device is updated. this feature does not have to be activated; any sectors usage as a write protected region is optional to the user. once the feature is enabled, the data in the protected sec- tors can no longer be erased or programmed when input levels of 5.5v or less are used. data in the remaining sec- tors can still be changed through the regular programming method. to activate the lockout feature, a series of six pro- gram commands to specific addresses with specific data must be performed. please refer to the command defini- tions table. sector programming lockout override: the user can override the sector programming lockout by taking the reset pin to 12v 0.5v. by doing this protected data can be altered through a chip erase, sector erase or byte/word programming. when the reset pin is brought back to ttl levels the sector programming lockout feature is again active. erase suspend/erase resume: the erase suspend command allows the system to interrupt a sector erase operation and then program or read data from a different sector within the same plane. since this device has a dual plane architecture, there is no need to use the erase sus- pend feature while erasing a sector when you want to read data from a sector in the other plane. after the erase sus- pend command is given, the device requires a maximum time of 15 m s to suspend the erase operation. after the erase operation has been suspended, the plane which con- tains the suspended sector enters the erase-suspend-read mode. the system can then read data or program data to any other sector within the device. an address is not required during the erase suspend command. during a sector erase suspend, another sector cannot be erased. to resume the sector erase operation, the system must write the erase resume command. the erase resume command is a one bus cycle command, which does require the plane address (determined by a18 and a19). the device also supports an erase suspend during a complete chip erase. while the chip erase is suspended, the user can read from any sector within the memory that is protected. the com- mand sequence for a chip erase suspend and a sector erase suspend are the same. product identification: the product identification mode identifies the device and manufacturer as atmel. it
at49bv16x4(t) 5 may be accessed by hardware or software operation. the hardware operation mode can be used by an external pro- grammer to identify the correct programming algorithm for the atmel product. for details, see operating modes (for hardware operation) or software product identification. the manufacturer and device code is the same for both modes. data polling: the at49bv16x4(t) features data polling to indicate the end of a program cycle. during a pro- gram cycle an attempted read of the last byte/word loaded will result in the complement of the loaded data on i/o7. once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. during a chip or sector erase operation, an attempt to read the device will give a 0 on i/o7. once the program or erase cycle has completed, true data will be read from the device. data polling may begin at any time during the program cycle. please see status bit table for more details. toggle bit: in addition to data polling the at49bv16x4(t) provides another method for determining the end of a program or erase cycle. during a program or erase operation, successive attempts to read data from the same memory plane will result in i/o6 toggling between one and zero. once the program cycle has completed, i/o6 will stop toggling and valid data will be read. examining the toggle bit may begin at any time during a program cycle. an additional toggle bit is available on i/o2 which can be used in conjunction with the toggle bit which is available on i/o6. while a sector is erase suspended, a read or a pro- gram operation from the suspended sector will result in the i/o2 bit toggling. please see status bit table for more details. rdy/busy : an open drain ready/busy output pin pro- vides another method of detecting the end of a program or erase operation. rdy/busy is actively pulled low during the internal program and erase cycles and is released at the completion of the cycle. the open drain connection allows for or-tying of several devices to the same rdy/busy line. hardware data protection: hardware features protect against inadvertent programs to the at49bv16x4(t) in the following ways: (a) v cc sense: if v cc is below 1.8v (typical), the program function is inhib- ited. (b) v cc power on delay: once v cc has reached the v cc sense level, the device will automatically time out 10 ms (typical) before programming. (c) program inhibit: hold- ing any one of oe low, ce high or we high inhibits pro- gram cycles. (d) noise filter: pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a program cycle. input levels: while operating with a 2.7v to 3.6v power supply, the address inputs and control inputs (oe , ce , and we ) may be driven from 0 to 5.5v without adversely affecting the operation of the device. the i/o lines can only be driven from 0 to v cc + 0.6v. output levels: output high levels (v oh ) are equal to v ccq - 0.2v (not v cc ). for 2.7v - 3.6v output levels, v ccq must be tied to v cc . for 1.8v - 2.2v output levels, v ccq must be regulated to 2.0v 10% while v cc must be regu- lated to 2.7v - 3.0v (for minimum power).
at49bv16x4(t) 6 notes: 1. the data format in each bus cycle is as follows: i/o15 - i/o8 (dont care); i/o7 - i/o0 (hex). the address format in each bus cycle is as follows: a15 - a0 (hex), a-1, a14 - a19 (dont care). 2. either one of the product id exit commands can be used. 3. sa = sector address. any byte/word address within a sector can be used to designate the sector address (see next four pages for details). 4. when the sector programming lockout feature is not enabled, the sector will erase (from the same sector erase command). once the sector has been protected, data in the protected sectors cannot be changed unless the reset pin is taken to 12v 0.5v. 5. pa is the plane address (a19 - a18). command definition in (hex) (1) command sequence bus cycles 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle addr data addr data addr data addr data addr data addr data read 1 addr d out chip erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 10 sector erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 sa (3)(4) 30 byte/word program 4 5555 aa 2aaa 55 5555 a0 addr d in bypass unlock 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 a0 single pulse byte/word program 1 addr d in sector lockout 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 sa (3)(4) 40 erase suspend 1 xxxx b0 erase resume 1 pa (5) 30 product id entry 3 5555 aa 2aaa 55 5555 90 product id exit (2) 3 5555 aa 2aaa 55 5555 f0 product id exit (2) 1 xxxx f0 absolute maximum ratings* temperature under bias................................ -55c to +125c *notice: stresses beyond those listed under absolute maximum ratings may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65c to +150c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v voltage on oe with respect to ground ...................................-0.6v to +13.5v
at49bv16x4(t) 7 memory plane a - bottom boot sector size (bytes/words) x8 address range (a19 - a-1) x16 address range (a19 - a0) sa0 8k/4k 000000 - 001fff 00000 - 00fff sa1 8k/4k 002000 - 003fff 01000 - 01fff sa2 8k/4k 004000 - 005fff 02000 - 02fff sa3 8k/4k 006000 - 007fff 03000 - 03fff sa4 8k/4k 008000 - 009fff 04000 - 04fff sa5 8k/4k 00a000 - 00bfff 05000 - 05fff sa6 8k/4k 00c000 - 00dfff 06000 - 06fff sa7 8k/4k 00e000 - 00ffff 07000 - 07fff sa8 32k/16k 010000 - 017fff 08000 - 0bfff sa9 32k/16k 018000 - 01ffff 0c000 - 0ffff sa10 64k/32k 020000 - 02ffff 10000 - 17fff sa11 64k/32k 030000 - 03ffff 18000 - 1ffff sa12 64k/32k 040000 - 04ffff 20000 - 27fff sa13 64k/32k 050000 - 05ffff 28000 - 2ffff sa14 64k/32k 060000 - 06ffff 30000 - 37fff sa15 64k/32k 070000 - 07ffff 38000 - 3ffff
at49bv16x4(t) 8 memory plane b - bottom boot sector size (bytes/words) x8 address range (a19 - a-1) x16 address range (a19 - a0) sa16 64k/32k 080000 - 08ffff 40000 - 47fff sa17 64k/32k 090000 - 09ffff 48000 - 4ffff sa18 64k/32k 0a0000 - 0affff 50000 - 57fff sa19 64k/32k 0b0000 - 0bffff 58000 - 5ffff sa20 64k/32k 0c0000 - 0cffff 60000 - 67fff sa21 64k/32k 0d0000 - 0dffff 68000 - 6ffff sa22 64k/32k 0e0000 - 0effff 70000 - 77fff sa23 64k/32k 0f0000 - 0fffff 78000 - 7ffff sa24 64k/32k 100000 - 10ffff 80000 - 87fff sa25 64k/32k 110000 - 11ffff 88000 - 8ffff sa26 64k/32k 120000 - 12ffff 90000 - 97fff sa27 64k/32k 130000 - 13ffff 98000 - 9ffff sa28 64k/32k 140000 - 14ffff a0000 - a7fff sa29 64k/32k 150000 - 15ffff a8000 - affff sa30 64k/32k 160000 - 16ffff b0000 - b7fff sa31 64k/32k 170000 - 17ffff b8000 - bffff sa32 64k/32k 180000 - 18ffff c0000 - c7fff sa33 64k/32k 190000 - 19ffff c8000 - cffff sa34 64k/32k 1a0000 - 1affff d0000 - d7fff sa35 64k/32k 1b0000 - 1bffff d8000 - dffff sa36 64k/32k 1c0000 - 1cffff e0000 - e7fff sa37 64k/32k 1d0000 - 1dffff e8000 - effff sa38 64k/32k 1e0000 - 1effff f0000 - f7fff sa39 64k/32k 1f0000 - 1fffff f8000 - fffff
at49bv16x4(t) 9 memory plane b - top boot sector size (bytes/words) x8 address range (a19 - a-1) x16 address range (a19 - a0) sa0 64k/32k 000000 - 00ffff 00000 - 07fff sa1 64k/32k 010000 - 01ffff 08000 - 0ffff sa2 64k/32k 020000 - 02ffff 10000 - 17fff sa3 64k/32k 030000 - 03ffff 18000 - 1ffff sa4 64k/32k 040000 - 04ffff 20000 - 27fff sa5 64k/32k 050000 - 05ffff 28000 - 2ffff sa6 64k/32k 060000 - 06ffff 30000 - 37fff sa7 64k/32k 070000 - 07ffff 38000 - 3ffff sa8 64k/32k 080000 - 08ffff 40000 - 47fff sa9 64k/32k 090000 - 09ffff 48000 - 4ffff sa10 64k/32k 0a0000 - 0affff 50000 - 57fff sa11 64k/32k 0b0000 - 0bffff 58000 - 5ffff sa12 64k/32k 0c0000 - 0cffff 60000 - 67fff sa13 64k/32k 0d0000 - 0dffff 68000 - 6ffff sa14 64k/32k 0e0000 - 0effff 70000 - 77fff sa15 64k/32k 0f0000 - 0fffff 78000 - 7ffff sa16 64k/32k 100000 - 10ffff 80000 - 87fff sa17 64k/32k 110000 - 11ffff 88000 - 8ffff sa18 64k/32k 120000 - 12ffff 90000 - 97fff sa19 64k/32k 130000 - 13ffff 98000 - 9ffff sa20 64k/32k 140000 - 14ffff a0000 - a7fff sa21 64k/32k 150000 - 15ffff a8000 - affff sa22 64k/32k 160000 - 16ffff b0000 - b7fff sa23 64k/32k 170000 - 17ffff b8000 - bffff
at49bv16x4(t) 10 memory plane a - top boot sector size (bytes/words) x8 address range (a19 - a-1) x16 address range (a19 - a0) sa24 64k/32k 180000 - 18ffff c0000 - c7fff sa25 64k/32k 190000 - 19ffff c8000 - cffff sa26 64k/32k 1a0000 - 1affff d0000 - d7fff sa27 64k/32k 1b0000 - 1bffff d8000 - dffff sa28 64k/32k 1c0000 - 1cffff e0000 - e7fff sa29 64k/32k 1d0000 - 1dffff e8000 - effff sa30 32k/16k 1e0000 - 1e7fff f0000 - f3fff sa31 32k/16k 1e8000 - 1effff f4000 - f7fff sa32 8k/4k 1f0000 - 1f1fff f8000 - f8fff sa33 8k/4k 1f2000 - 1f3fff f9000 - f9fff sa34 8k/4k 1f4000 - 1f5fff fa000 - fafff sa35 8k/4k 1f6000 - 1f7fff fb000 - fbfff sa36 8k/4k 1f8000 - 1f9fff fc000 - fcfff sa37 8k/4k 1fa000 - 1fbfff fd000 - fdfff sa38 8k/4k 1fc000 - 1fdfff fe000 - fefff sa39 8k/4k 1fe000 - 1fffff ff000 - fffff
at49bv16x4(t) 11 operating modes notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. 3. v h = 12.0v 0.5v. 4. manufacturer code: 1fh (x8); 161f (x16), device code: c0h (x8); 16co (x16). 5. see details under software product identification entry/exit. 6. the use of the v pp pin is optional. note: 1. in the erase mode, i cc is 50 ma. dc and ac operating range at49bv16x4-90 at49bv16x4-12 operating temperature (case) com. 0c - 70c 0c - 70c ind. -40c - 85c -40c - 85c v cc power supply 2.7v to 3.6v 2.7v to 3.6v mode ce oe we reset v pp (6) ai i/o read v il v il v ih v ih xaid out program/ erase (2) v il v ih v il v ih 5v 10% ai d in standby/program inhibit v ih x (1) xv ih x x high z program inhibit x x v ih v ih v il program inhibit x v il xv ih v il output disable x v ih xv ih x high z reset x x x v il x x high z product identification hardware v il v il v ih v ih a1 - a19 = v il , a9 = v h (3) a0 = v il manufacturer code (4) a1 - a19 = v il , a9 = v h (3) a0 = v ih device code (4) software (5) v ih a0 = v il , a1 - a19 = v il manufacturer code (4) a0 = v ih , a1 - a19 = v il device code (4) dc characteristics symbol parameter condition min max units i li input load current v in = 0v to v cc 10 m a i lo output leakage current v i/o = 0v to v cc 10 m a i sb1 v cc standby current cmos ce = v cc - 0.3v to v cc 10 m a i sb2 v cc standby current ttl ce = 2.0v to v cc 1ma i cc (1) v cc active current f = 5 mhz; i out = 0 ma 25 ma i ccrw v cc read while write current f = 5 mhz; i out = 0 ma 50 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol = 2.1 ma 0.45 v v oh output high voltage i oh = -400 m a2.4v
at49bv16x4(t) 12 ac read waveforms (1)(2)(3)(4) notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce whichever occurs first (cl = 5 pf). 4. this parameter is characterized and is not 100% tested. input test waveforms and measurement level t r , t f < 5 ns output test load note: 1. this parameter is characterized and is not 100% tested. ac read characteristics symbol parameter at49bv16x4-90 at49bv16x4-12 units min max min max t acc address to output delay 90 120 ns t ce (1) ce to output delay 90 120 ns t oe (2) oe to output delay 0 40 0 50 ns t df (3)(4) ce or oe to output float 0 25 0 30 ns t oh output hold from oe , ce or address, whichever occurred first 0 0 ns t ro reset to output delay 800 800 ns output valid output high z reset oe toe tce address valid tdf toh tacc tro ce address pin capacitance f = 1 mhz, t = 25c (1) typ max units conditions c in 46 pfv in = 0v c out 812 pfv out = 0v
at49bv16x4(t) 13 ac byte/word load waveforms we controlled ce controlled ac byte/word load characteristics symbol parameter min max units t as , t oes address, oe set-up time 10 ns t ah address hold time 100 ns t cs chip select set-up time 0 ns t ch chip select hold time 0 ns t wp write pulse width (we or ce )100ns t ds data set-up time 100 ns t dh , t oeh data, oe hold time 10 ns t wph write pulse width high 50 ns
at49bv16x4(t) 14 program cycle waveforms sector or chip erase cycle waveforms notes: 1. oe must be high only when we and ce are both low. 2. for chip erase, the address should be 5555. for sector erase, the address depends on what sector is to be erased. (see note 3 under command definitions.) 3. for chip erase, the data should be 10h, and for sector erase, the data should be 30h. program cycle characteristics symbol parameter min typ max units t bp byte/word programming time 20 50 m s t as address set-up time 0 ns t ah address hold time 100 ns t ds data set-up time 100 ns t dh data hold time 0 ns t wp write pulse width 100 ns t wph write pulse width high 50 ns t ec chip erase cycle time 10 seconds t sec sector erase cycle time 200 ms oe program cycle input data address a0 55 5555 5555 aa 2aaa t bp t wph t wp ce we a0 -a19 data t as t ah t dh t ds 5555 aa oe (1) aa 80 note 3 55 55 5555 5555 note 2 aa word 0 word 1 word 2 word 3 word 4 word 5 2aaa 2aaa t wph t wp ce we a0-a19 data t as t ah t ec t dh t ds 5555
at49bv16x4(t) 15 notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. data polling waveforms toggle bit characteristics (1) notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. toggle bit waveforms (1)(2)(3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. the t oehp specification must be met by the toggling input(s). 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. data polling characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns
at49bv16x4(t) 16 status bit table status bit i/o 7 i/o 6 i/o 2 read address in plane a plane b plane a plane b plane a plane b while programming in plane a i/o7 data toggle data 1 data programming in plane b data i/o7 data toggle data 1 erasing in plane a 0 data toggle data toggle data erasing in plane b data 0 data toggle data toggle erase suspended & read erasing sector 1 1 1 1 toggle toggle erase suspended & read non-erasing sector data data data data data data erase suspended & program erasing sector 1 1 1 1 toggle toggle erase suspended & program non-erasing sector in plane a i/o7 data toggle data toggle data erase suspended & program non-erasing sector in plane b data i/o7 data toggle data toggle
at49bv16x4(t) 17 ordering information t acc (ns) i cc (ma) ordering code package operation range active standby 90 25 0.01 AT49BV1604-90tc AT49BV1604-90uc 48t 48u commercial (0 to 70 c) at49bv1614-90cc at49bv1614-90tc 48c2 48t 25 0.01 AT49BV1604-90ti AT49BV1604-90ui 48t 48u industrial (-40 to 85 c) at49bv1614-90ci at49bv1614-90ti 48c2 48t 120 25 0.01 AT49BV1604-12tc AT49BV1604-12uc 48t 48u commercial (0 to 70 c) at49bv1614-12cc at49bv1614-12tc 48c2 48t 25 0.01 AT49BV1604-12ti AT49BV1604-12ui 48t 48u industrial (-40 to 85 c) at49bv1614-12ci at49bv1614-12ti 48c2 48t 90 25 0.01 AT49BV1604t-90tc AT49BV1604t-90uc 48t 48u commercial (0 to 70 c) at49bv1614t-90cc at49bv1614t-90tc 48c2 48t 25 0.01 AT49BV1604t-90ti AT49BV1604t-90ui 48t 48u industrial (-40 to 85 c) at49bv1614t-90ci at49bv1614t-90ti 48c2 48t 120 25 0.01 AT49BV1604t-12tc AT49BV1604t-12uc 48t 48u commercial (0 to 70 c) at49bv1614t-12cc at49bv1614t-12tc 48c2 48t 25 0.01 AT49BV1604t-12ti AT49BV1604t-12ui 48t 48u industrial (-40 to 85 c) at49bv1614t-12ci at49bv1614t-12ti 48c2 48t package type 48c2 48-ball, plastic chip-size ball grid array package (cbga) 48t 48-lead, thin small outline package (tsop) 48u 48-ball, micro ball grid array package ( m bga)
at49bv16x4(t) 18 packaging information a b c d e f g h 6 54321 5.6 non-accumulative 0.40 dia typ 4.0 8.2 7.8 1.2 max 0.35 11.2 10.8 0.85 0.75 typ *controlling dimension: millimeters 1 2 3 4 5 6 7 8 fedcba 5.25 8.4 8.0 non-accumulative 0.30 dia typ 3.75 6.8 6.4 0.70 0.15 min. 0.75 typ 1.00 0.85 48c2, 48-ball, plastic chip-size ball grid array package (cbga) 48t, 48-lead, plastic thin small outline package (tsop) dimensions in millimeters and (inches)* jedec outline mo-142 dd 48u, 48-ball, micro ball grid array package ( m bga)

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